Verilog HDL


4 bit ring counter

An example of 4 bit counter in Verilog-HDL

Top module for test.
module top;
reg reset;
reg clk;
wire [15:0] count_out;

counter count_1(reset, clk, count_out);

initial begin
	clk=0;
	reset=1;
	#10 reset=0;
	#100;
	$stop;
end

initial begin
	forever
		#1 clk=~clk;
end

always@(negedge clk) begin
	 $display( "Time=%d  count_out=%b",$time, count_out);
end

endmodule



4 bit counter in Verilog-HDL

module counter(reset, clk, count_out); input reset; input clk; reg [3:0] count; output [15:0] count_out; wire [15:0] count_out; assign count_out=f_decode(count); function [15:0] f_decode; input [3:0] count; begin case ( count ) 4'b0000 : f_decode=16'b0000000000000001; 4'b0001 : f_decode=16'b0000000000000010; 4'b0010 : f_decode=16'b0000000000000100; 4'b0011 : f_decode=16'b0000000000001000; 4'b0100 : f_decode=16'b0000000000010000; 4'b0101 : f_decode=16'b0000000000100000; 4'b0110 : f_decode=16'b0000000001000000; 4'b0111 : f_decode=16'b0000000010000000; 4'b1000 : f_decode=16'b0000000100000000; 4'b1001 : f_decode=16'b0000001000000000; 4'b1010 : f_decode=16'b0000010000000000; 4'b1011 : f_decode=16'b0000100000000000; 4'b1100 : f_decode=16'b0001000000000000; 4'b1101 : f_decode=16'b0010000000000000; 4'b1110 : f_decode=16'b0100000000000000; 4'b1111 : f_decode=16'b1000000000000000; default : f_decode=16'b0000000000000001; endcase end endfunction always@(posedge clk) begin if (reset==1) begin count=0; end else begin if (count == 4'b1111) begin count=4'b0000; end else begin count=count+1; end end end endmodule


Result of Simulation

Time=2	count_out=0000000000000001
Time=4	count_out=0000000000000001
Time=6	count_out=0000000000000001
Time=8	count_out=0000000000000001
Time=10	 count_out=0000000000000001
Time=12	 count_out=0000000000000010
Time=14	 count_out=0000000000000100
Time=16	 count_out=0000000000001000
Time=18	 count_out=0000000000010000
Time=20	 count_out=0000000000100000
Time=22	 count_out=0000000001000000
Time=24	 count_out=0000000010000000
Time=26	 count_out=0000000100000000
Time=28	 count_out=0000001000000000
Time=30	 count_out=0000010000000000
Time=32	 count_out=0000100000000000
Time=34	 count_out=0001000000000000
Time=36	 count_out=0010000000000000
Time=38	 count_out=0100000000000000
Time=40	 count_out=1000000000000000
Time=42	 count_out=0000000000000001
Time=44	 count_out=0000000000000010
Time=46	 count_out=0000000000000100
Time=48	 count_out=0000000000001000
Time=50	 count_out=0000000000010000
Time=52	 count_out=0000000000100000
Time=54	 count_out=0000000001000000
Time=56	 count_out=0000000010000000
Time=58	 count_out=0000000100000000
Time=60	 count_out=0000001000000000
Time=62	 count_out=0000010000000000
Time=64	 count_out=0000100000000000
Time=66	 count_out=0001000000000000
Time=68	 count_out=0010000000000000
Time=70	 count_out=0100000000000000
Time=72	 count_out=1000000000000000
Time=74	 count_out=0000000000000001
Time=76	 count_out=0000000000000010
Time=78	 count_out=0000000000000100
Time=80	 count_out=0000000000001000
Time=82	 count_out=0000000000010000
Time=84	 count_out=0000000000100000
Time=86	 count_out=0000000001000000
Time=88	 count_out=0000000010000000
Time=90	 count_out=0000000100000000
Time=92	 count_out=0000001000000000
Time=94	 count_out=0000010000000000
Time=96	 count_out=0000100000000000
Time=98	 count_out=0001000000000000
Time=100  count_out=0010000000000000
Time=102  count_out=0100000000000000
Time=104  count_out=1000000000000000
Time=106  count_out=0000000000000001
Time=108  count_out=0000000000000010
Time=110  count_out=0000000000000100


Time chart


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